Peripheral storage hierarchies have been used for years for providing an apparent store as suggested by Eden, et al in U.S. Pat. No. 3,569,938. Eden, et al teach that, in a demand paging or request system, caching data in a cache-type high-speed front store (buffer) can make a peripheral storage system appear to have a large capacity yet provide rapid access to data, rapid access being faster than that provided to the normal backing store. Eden, et al also teach that the backing store can be a retentive store, such as magnetic tape recorders and magnetic disk recorders, while the front store can be a volatile store such as a magnetic core store. With the advances in data storage technology, the front store typically includes semiconductive-type data storage elements. U.S. Pat. No. 3,839,704 shows another form of the storage hierarchy.
An important aspect of storage hierarchies is enabling data integrity. That is, the data received from a user, such as a central processing unit (CPU) or other data handling device, should be returned to the supplying unit either correct or with an indication that errors may exist. Also, it is typical practice in storage hierarchies to move data from a higher level to a lower level for such retentive storage, as well as to limit the data in the higher levels such that other data can be stored for rapid access. U.S. Pat. No. 4,020,466 shows copying changes from a high-level store to a backing store, while U.S. Pat. No. 4,077,059 shows forcing copy-back under predetermined conditions. Such copy-back operations can consume storage hierarchy performance time, i.e., so much data may be copied back that access to the data by a using unit may be degraded. This problem is partially solved by U.S. Pat. No. 3,588,839, which teaches that the only data that need be copied back from a high-level storage unit to a low-level storage unit is that data that is altered, i.e., where there is noncongruence between data in a backing store and data in a front store.
Storage hierarchies have taken diverse forms. For example, in accordance with the Eden, et al U.S. Pat. No. 3,569,938, a single high-speed store serviced several users. U.S. Pat. No. 3,735,360 shows that each processor can have its own high-speed store, or cache, for different performance reasons. Performance of the storage hierarchies also is affected by the algorithms and other controls used to place predetermined data into the cache, or high-speed storage portion. Accordingly, U.S. Pat. No. 3,898,624 shows that varying the time of fetching data from a backing store to a front, or caching, store can be selected by the computer operator in accordance with the programs being executed in a using CPU. In this manner, it is hoped that the data resident in the cache or upper level of the hierarchy will be that data needed by the CPU, while excess data not needed is not resident; this arrangement allows more useful data to be stored in the higher level storage portion. All of these operations become quite intricate. Accordingly, evaluation programs for storage hierarchies have been used to evaluate how best to manage a storage hierarchy. U.S. Pat. Nos. 3,964,028 and 4,068,304 show performance monitoring of storage hierarchies for achieving these goals. Even at that, much remains to be done in various types of storage hierarchies for enhancing optimum performance while ensuring data integrity. Much of the work with respect to storage hierarchies has occurred in the cache and main memory combinations connected to a using CPU. The principles and teachings from a cached main memory relate direction to caching and buffering peripheral system, as originally suggested by Eden et al, supra. Of course, main memory has been used prior to Eden et al for buffering or caching data from a magnetic tape and disk unit for a CPU, i.e., a main memory was not only used as a CPU working store but also as a buffer for peripheral devices.
The performance monitoring referred to above has indicated that it is not always in the best interest of total data processing performance and integrity to use a caching buffer interposed between a using unit and a backing store. For example, U.S. Pat. No. 4,075,686 teaches that a cache can be turned on and off by special instructions for bypassing the cache. Further, the backing store or memory was segmented into various devices with some of the devices, or segments, being bypassed, such as for serial or sequential input-output operations. This patent further teaches that, for certain commands, it is more desirable to not use cache than to use cache. U.S. Pat. No. 4,268,907 teaches that, for a command specifying the fetching of data words, an indicator flag is set to a predetermined state. Such indicator flag causes data transfer circuits to respond to subsequent predetermined commands to bypass cache storage. This bypass prevents replacement (flushing) of data instructions stored in cache during the execution of long serial data transfers. Further, U.S. Pat. No. 4,189,770 shows bypassing cache for operands, but using cache for storing instructions.
In some storage hierarchies, data integrity is ensured by transferring data to both the cache and a backing store whenever data is written to the memory. As an example see U.S. Pat. No. 4,045,781. While in many instances this may prove valuable, it does tend to have high data occupancy in the cache which may have adverse effects on total performance in certain applications. U.S. Pat. No. 4,173,781 describes a table control system for ensuring coherence between various levels in a storage hierarchy. Several storage hierarchies have involved updating a backing store after updating a cache, such as in U.S. Pat. No. 4,167,782, or controlling the updating of the cache when the memory is updated, such as shown in U.S. Pat. No. 4,157,586. Other systems always write to cache once data is resident in cache, or have space allocated in cache as taught by U.S. Pat. No. 4,084,234. For data integrity, changes to data in a cache are usually copied back to a lower level, or backing store, such as shown in U.S. Pat. No. 4,020,466. In a multilevel storage hierarchy including a direct access storage device (DASD), also termed a disk data storage device, having an electronic random-access memory cache, it is desired to always have data written to the DASD, which is a retentive memory, as soon as possible. Such writing ensures data integrity by storing data in a retentive memory as opposed to storing data only in a volatile electronic random-access memory.